(1) Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more particularly, to a semiconductor device to which a stress technique is applied and a method of manufacturing such a semiconductor device.
(2) Description of the Related Art
In recent years attention has been riveted on what is called a stress technique as a technique for realizing a high speed without performing microfabrication. Carrier mobility can be improved by using this stress technique.
For example, a technique for forming portions of a source and a drain of a p-channel MOS field-effect transistor (pMOS transistor) formed over a silicon (Si) substrate by the use of a silicon germanium (SiGe) layer which differs from the Si substrate in lattice constant and for improving hole mobility by creating a compressive stress in a channel region is proposed.
Even if nickel silicide or cobalt silicide is formed in a pMOS transistor in which silicon germanium is used or an nMOS transistor in which silicon carbide (SiC) is used in order to reduce the resistance of a source and a drain, it is necessary to reduce a leakage current of the pMOS transistor or the nMOS transistor.